1. Field of the Invention
The present invention relates to a substrate and manufacturing method thereof. More particularly, the present invention relates to a flip chip package substrate and manufacturing method thereof.
2. Description of the Related Art
In the packaging process of integrated circuits (IC), the first level packaging mainly involves attaching chips onto carriers. The packaging formats include wire bonding (WB), tape automatic bonding (TAB) and flip chip (FC). Regardless of TAB or FC formats, in the process of attaching the chip onto the package substrate, bumps are fabricated on the bonding pads of a wafer so that the bumps can subsequently serve as an electrical connection between the chip and package substrate.
With the maturity of the fabricating technology of semiconductor devices, the pitch between the bumps on a chip has been shrinking. However, the fabricating technology of the package substrate can hardly keep up with that of the chips. At present, the smallest pitch between the bumps on a chip is down to about 120 microns. Yet, the pitch between bonding pads on a package substrate fabricated with the highest precision is at most 200 microns. Therefore, the current fabricating technology of the packaging substrate limits the bump pitch on a chip. Furthermore, as the pad pitch continues to reduce, the mismatch of the coefficient of thermal expansion between the chip and the package substrate often leads to increasing thermal stress and warpage between the two. Ultimately, the reliability of the connection between the chip and the package substrate declines. In addition, the cost of fabricating a package substrate with fine pad pitch is very high.